This invention relates to a semiconductor device which has an InP layer and a method of manufacturing the semiconductor device.
Compared with GaAs, InP has been recognized as an attractive material for channels of power semiconductor devices, such as a power field effect transistor (FET), because of its high peak electron velocity, high thermal conductivity, and high breakdown field. Several types of the semiconductor devices have been reported as such one having an InP channel, those are MESFET, MISFET, Retero MISFET, and the like.
Conventionally, in processes of manufacturing MESFET, wet-etching is employed as a pre-process before growing a passivation film or a spacer layer. However, the MESFET having the InP channel thus manufactured do not have a good pinch-off characteristic. This is because the pre-process technique employing an wet-etchant for the passivation film or the spacer layer is immature. Namely, an InP oxide film including In.sub.2 O.sub.3 is formed in an interface between an InP substrate and such a passivation film or a spacer layer, so that an interface leak current is increased therebetween. A similar problem is reported in Applied Physics Letters, pages 163 to 165, volume 37, 1980. As taught by the above-referenced paper, the InP oxide film including the In.sub.2 O.sub.3 is a conductive metal oxide film.
On the other hand, a conventional MISFET or Hetero MISFET comprises a thick silicon oxide or a thick hetero semiconductor crystal inserted between a gate and a shotkey layer for the purpose of reducing leak current from the gate. Further, the conventional MISFET or Hetero MISFET also comprises a thick insulation film or a thick hetero semiconductor crystal interposed between a metal gate and a channel for the purpose of improving gate breakdown voltage. As a result, a distance therebetween becomes large and decreases mutual conductance.
Moreover, when a hetero semiconductor crystal lattice-mismatched to the InP is employed as a Schottky layer on the InP substrate in the Hetero MISFET, dislocation or interface state due to lattice-mismatching is inevitably caused to occur. Leak current flowing through the Schottky layer is generated to decrease the aforesaid gate breakdown voltage. Furthermore, occurs that frequency is dispersed and mutual conductance is decreased the upper portions.
In the conventional Hetero MISFET, the InP layer and the hetero semiconductor crystal including no P (phosphorous) are continuously grown by the use of molecular beam epitaxiy (MBE) or metal organic chemical vapor deposition (MOCVD), a source of phosphorous must be changed. However, it is very difficult to control the flow of phosphorous, because of its extremely high vapor pressure. Consequently, a steep hetero interface cannot be obtained in the conventional Hetero MISFET. Accordingly, a conduction band profile is disarranged. Particularly, when the hetero semiconductor crystal including no phosphorous is grown on the InP layer, an electron transfer characteristic in the InP layer is deteriorated.